Cache coherence refers to uniformity of data stored in multiple memory locations such as caches or backing memory (e.g., dynamic random access memory or “DRAM”) in processing systems such as a multiprocessor or multi-core processing systems wherein multiple clients (e.g., processors/cores) can access and share data which is ultimately stored in a common memory (e.g., the DRAM). Referring, for example to processing system 100 of FIG. 1, clients 102a-b may have respective caches 104a-b, and a backing storage shown as memory 106. Clients 102a-b may read data from or store data to memory 106, with caches 104a-b acting as respective intermediate storage locations for fast access.
Cache coherency mechanisms generally depicted with the reference numeral 105 may be employed to avoid violation of coherence between cached copies of data associated with a given memory location in memory 106. Known cache coherency mechanisms 105 include snooping, wherein each one of caches 104a-b (or by means of processors, e.g. clients 102a-b) may monitor the other for accesses to addresses cached and ensure coherence. Coherence may be ensured by mechanisms such as cache flushing, cache sharing, etc.
Cache coherence mechanisms may be complicated by situations wherein the data stored in memory 106 can be associated with addresses. A situation wherein the data may have different addresses involves address apertures. An address aperture provides access to the same memory region through an alternative address range. Modern processors (e.g., clients 102a-b) may use virtual addresses which are translated to physical addresses of the data stored in memory 106. These virtual addresses may also be referred to as aliased addresses. Typically, there may be a simple mapping between aperture addresses and the aliased addresses for the same physical memory locations.
However, in instances wherein the address apertures are functional address apertures, the mapping may be more complex. A functional address aperture is an aperture which performs some function on the data as it passes through the aperture. Referring to processing system 200 of FIG. 2, processor 202 may access memory 206 (e.g., through memory bus 208) using aliased address 212 or through functional address aperture 204, wherein function 205 is performed on data addressed using aperture address 210.
Examples of function 205 include encryption, compression, error-correction, etc. Function 205 may introduce a complex mapping between data in aperture address domain (i.e., addressed using aperture address 210) and in aliased address domain (i.e., addressed using aliased address 212). The address mapping between aperture address 210 and aliased address 212 may not be in a direct or one-to-one correspondence. In some instances, an address region in the aperture address domain may correspond to a smaller or larger region in the aliased address domain, e.g., as in the case of functional address aperture 204 implementing compression as function 205.
Accordingly, a single access in the aperture address domain may correspond to zero, one, or more than one accesses in the aliased address domain. The accesses may even be to non-contiguous memory regions of memory 206, e.g., as in the case of functional address aperture 204 implementing error-control coding (ECC) as function 205, wherein parity bits for the ECC for data in a buffer or memory region may be stored in a separate buffer. Function 205 may also include memory or caching such that accesses in the aperture space are delayed or coalesced.
As will be appreciated from the above discussion, functional address apertures may give rise to new and complex demands on coherency between the aperture address domain and aliased address domain. There is a corresponding need in the art to meet these demands for efficiently handling the coherency between the aperture address domain and aliased address domain.